wafer.space Community - PEX for taps

7:17 a.m.

I'm not sure it will change anything at all.

Yeah right, I think namibj told me earlier that the substrate is not really simulated properly.

7:22 a.m.

I've drawn my tap cells like those generated in klayout (on one side, made of psd/psc) but I feel like I don't really know what I am doing and hoping that simulations can later spot my issues.

I wouldn't count on it.

7:23 a.m.

But wether that matters or not depends a lot of what you're doing.

7:25 a.m.

My understanding is it's mostly about tiny noise and cross talk between circuits, catching stray substrate currents. If you're circuit isn't super low noise or that sensitive, should be just fine (edited)

7:25 a.m.

Just my 2 ct. (edited)

Appreciate all cents i can get

I'm fine with a bit of noise. Its mostly latch-up I want to be sure I avoid, but maybe its not such a large problem. I have been browsing some designs and I think my method is fine.

Latchup you should be fine. The DRC will check there are enough taps and if there are wired to the proper rail it's all good.